1. Field of the Invention
The present invention generally relates to the generation of clock trees for circuit designs, and more particularly relates to a method and apparatus for distributing clock drivers within a hierarchical circuit design.
2. Description of the Prior Art
The advancement of integrated circuit, printed circuit board and other related technologies is progressing at a very rapid rate. The latest generation of integrated circuits can incorporate over four times the circuitry than was possible just a few years ago. Further, circuit board and multi-chip module technology has allowed much denser circuit board designs. These and other advancements have allowed the development of increasingly complex and high speed computer systems.
The design of such computer systems has become increasingly difficult and time consuming. To maximize performance and minimize the size and power of such computer system, system designers often implement much of the hardware in a number of integrated circuits. For maximum performance, the integrated circuits are often custom or semi-custom designed. Each integrated circuit may contain several hundred thousand gates, and each gate must be placed and routed in accordance with an overall computer system specification, all on a die typically measuring less than 625 mils on a side.
The overall system specification typically defines the overall function of the computer system, including the power and timing requirements thereof. Because of the size and complexity of such computer systems, system designers often partition the overall design into a number of blocks, wherein each of the blocks performs a dedicated function. Partitioning is typically continued until the size of each of the sub-blocks is of a manageable size. A specification for each of the sub-blocks is then written to define the function, timing and power requirements thereof. Often, several of the sub-blocks are implemented in an integrated circuit.
Most circuit design databases are hierarchical in nature. Thus, a circuit design database may include a number of regions, including a first level region. The first level region may reference a number of second level regions. A higher level region is typically called the parent of each of the next lower level regions. Likewise, the lower level regions are typically called the children of the corresponding higher level region. The lowest level in the design hierarchy typically includes only basic library components (e.g. leaf cells).
Once the design is described in a detailed form the circuit design may be placed and routed on a scaled representation of an integrated circuit die. This may be accomplished using an automatic place and route tool. However, because automatic placement tools may not yield an optimum design solution, particularly for high performance designs that have strict timing and physical requirements, circuit designers often manually place critical circuit objects (e.g. cells and/or regions). This may be accomplished by using a commercially available placement tool (also known as a floor planning tool), typically implemented in software. The placement tool may include a graphics terminal that displays various information about the circuit design, often in several different windows.
Using a placement tool, circuit designers may perform preliminary placement by first placing selected regions. In some placement tools, the outer boundaries of the regions are appropriately sized to accommodate all underlying objects. Thus, the circuit designer may rely on an automated placement tool to place the underlying objects within the outer boundary. If more detailed placement is required because of timing, physical or other constraints, selected lower level regions or cells may be manually placed by the circuit designer.
Each integrated circuit typically includes a clock tree. The clock tree distributes one or more clock signals throughout the design. A primary goal of a clock tree is to minimize clock skew between clocked elements. That is, clock skew may reduce the time allowed for certain logic paths within the design, and thus may reduce the performance of the design. Thus, for high performance designs that have strict timing requirements, it is often critical to minimize clock skew.
To minimize clock skew, typical clock trees include a number of clock drivers that are symmetrically and evenly placed on the integrated circuit die. There may be a number of first level drivers, which may receive a clock signal from an input buffer, and may be placed near the center of the integrated circuit. Each of the first level drivers may drive a number of second level drivers. Typically, each of the first level drivers will drive the same number of second level drivers. This is intended to maintain a matched load therebetween. The number of second level drivers may be symmetrically and evenly placed on the integrated circuit die.
A typical clock tree may include a number of levels of clock drivers. The number of clock drivers in the last level is typically sufficient to drive all of the clock loads within the design. Like all other levels, the last level of clock drivers is typically placed symmetrically and evenly throughout the integrated circuit die.
In many cases, all of the clock drivers are pre-placed on the integrated circuit die. This allows the clock drivers to be placed at any desired location on the integrated circuit die. This allows the clock tree to be evenly distributed and balanced. The routing between clock drivers may also be pre-placed and balanced.
Designing and constructing a clock tree is often a time-consuming task, requiring significant design resources. Therefore, it is common for only one "worst case" clock tree to be designed. The "worst case" clock tree may then be used in each integrated circuit within a system, while still maintaining an acceptable clock skew.
After the "worst case" clock tree is designed and preplaced, the circuit designer may use a placement tool to manually place selected regions or cell of the circuit design. Thereafter, an automatic place and route tool may be used to place the remaining cells, and route the design according to the overall design specifications.
The above clock tree generating scheme has a number of limitations, some of which are described below. First, each of the clock drivers in the last level of the clock tree may have a limited drive capability, and thus may only drive a limited number of clock loads (e.g. registers, flip-flops, etc.). To use the same clock tree for multiple integrated circuit designs, and as described above, the clock tree may have to be designed to accommodate the number of clock loads in the "worst case" integrated circuit design. Because the same `worst case` clock tree may be used for all integrated circuits within the system, many of the integrated circuits may be populated with more clock drivers than are actually required. This is especially limiting when the number of clock drivers that are required varies dramatically between circuit designs. These extra clock drivers may consume die area and power that could otherwise be used to implement the logical design.
Second, and because the clock tree is generally symmetrically and evenly distributed throughout the integrated circuit die, the circuit designer typically must restrict the number of clock loads that are placed in a given region. That is, since only a set number of clock drivers are typically available in any one region, the circuit designer may not generally over-populate one region of the integrated circuit die with regions or cells that have high clock loads. This limitation sometimes forces the circuit designer to place clock loads within regions that contain available clock drivers, even if this reduces the performance of the system. Moreover, the circuit designer may not realize that a region has too many clock loads until after the automatic place and route step, or during a full verification step. This, in turn, may require another pass through the layout cycle.